RISC-V Reaches the Summit

RISC-V (and its ecosystem) is one of the fastest growing areas of the chip market. New processors and development kits are becoming available on a seemingly daily basis, and 2020 promises to be RISC-V’s biggest year yet. This week, the RISC-V Summit in San Jose, CA will provide a forum for developers to present the latest innovations in this burgeoning field. New chips and design resources will be on full display for the RISC-V community to size up for itself – here are just a couple new products that caught our eye…

Andes Technology, the Taiwan-based chip developer that primarily manufactures 32/64-bit embedded CPU cores, recently debuted the AndesCore 27-series, which the company boasts are the first licensable RISC-V cores to provide RISC-V vector instruction extension (RVV). Artificial intelligence, augmented/virtual reality and multimedia applications (among many others) that require complex processing of a large volume of data can be slowed by SIMD (single instruction, multi data) computer architectures that provide a narrower range of performance. By utilizing the RVV extension, Andes believes it can provide better performance and greater flexibility to developers through scalable data sizes and more malleable microarchitecture implementations. While production release isn’t scheduled until the first quarter of 2020, the first of the new cores has already been delivered to its initial licensee, which, according to the EE Times, plans to use it in a data center AI engine. “The RVV extension boldly takes RISC-V beyond any licensable processor core technology into the hottest markets today, and our licensee’s confidence in the R&D team enables Andes to be the first to deliver on this ambitious vision,” according to Frankwell Lin, President of Andes. The initial members of the 27-series will be the A27 (32-bit) and the AX27 and NX27V (64-bit). The A27 and AX27 are optimized for Linux-based applications and provide 50% higher memory bandwidth than their predecessors from the Andes 25-series, while NX27V implements a vector processing unit (VPU) that supports the RVV scalable vector instruction set.

As previously noted in this space, new chips aren’t the only indicator of RISC-V’s growth in the market. The ecosystem for developers working with RISC-V architecture has expanded as well, with new software and development tools being released to accompany new chips becoming standard-operating-procedure. Microchip Technology, Inc. announced at the RISC-V Summit that the company will be allowing “qualified” customers to enroll in their Early Access Program (EAP) for Microchip’s PolarFire SoC field programmable gate array (FPGA). The program will let developers use the company’s Librero SoC 12.3 FPGA design suite and SoftConsole 6.2 integrated development environment to experiment with the PolarFire SoC in their own designs. The company claims the chip is the first SoC FPGA with a deterministic RISC-V CPU cluster and L2 memory subsystem, making it an optimal solution for Linux plus real-time applications. The EAP is part of Microchip’s expanding “Mi-V” RISC-V ecosystem, a collection of resources and design tools the company has amassed with help from various partners across the industry to support the development of RISC-V technology for embedded systems. “Delivering the industry’s first RISC-V based SoC FPGA along with our Mi-V ecosystem, Microchip and its Mi-V partners are driving innovation in the embedded space, giving designers the ability to develop a whole new class of power-efficient applications,” boasts Bruce Weyer, VP of the FPGA business unit at Microchip. “This, in turn, will allow our clients to add unprecedented capabilities at the edge of the network for communications, defense, medical and industrial automation.”

Despite what the name might imply, RISC-V is anything but a risky bet. With new technology and design support systems becoming available on a seemingly daily basis, it’s the definition of a “growth industry.” We’ll keep checking in on RISC-V and where it’s headed in this space in the future – probably sooner rather than later.